A 0.8 μm CMOS, Double Polysilicon EEPROM Technology Module Optimized for Minimum Wafer Cost

A novel process technology has been developed for smart analog and mixed-signal products requiring embedded EEPROM. The technology is a modular addition to a 0.8 μm, single polysilicon, double metal baseline CMOS process. The EEPROM process architecture is defined with the primary goal of minimizing the number of additional process steps driven by wafer cost considerations. A double polysilicon architecture is chosen to allow for the formation of an integral, linear interpoly capacitor and to reduce the EEPROM cell size. The module requires 3 additional masks beyond those of the baseline CMOS and adds 20% to the wafer cost. An anti-lock braking system (ABS) chip with a 64 byte EEPROM core has been designed and fabricated to demonstrate the technology.