Design and testing of CMOS compatible EEPROM

A single-poly CMOS compatible Electrically Erasable Programmable Read-Only Memory (EEPROM) is presented in this paper. The difference between the traditional structure and the proposed structure is that the capacitance between control gate and floating gate, and the capacitance between floating gate and channel are fabricated on the same layer. This approach makes EEPROM and periphery circuits can be fabricated in the standard CMOS technology, so development cost is greatly reduced. An 8 byte × 8 bits EEPROM array including readout circuit and charge pump circuit is implemented in TSMC 0.35μm CMOS technology in this paper. Meanwhile, pre-charge scheme is used in the readout circuit.