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A 0.8 μm CMOS, Double Polysilicon EEPROM Technology Module Optimized for Minimum Wafer Cost

Cacharelis, Hoffstetter, Schmidt, Nilles, Gough, Smillie

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Key concepts: EEPROM, CMOS, Wafer, Materials science, Electrical engineering, EPROM, Electronic engineering, Polysilicon depletion effect

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