A Novel Integration Technology Of EEPROM Embedded CMOS Logic Vlsi Suitable For ASIC Applications

A novel process technology has been developed to fabricate an EEPROM embedded CMOS VLSI. The new technique utilizing a single poly-Si EEPROM cell reduces process steps by 25% as compared with the conventional double poly-Si EEPROM cell. The EEPROM-embedded CMOS LOGIC LSI can be shrunk over future technology generations by introducing three kinds of gate oxide thickness. A widely operating voltage ranging from 1.5 V to 6.0 V and a standby current below 100 nA have been achieved.