Simulation-based solution of load-balancing problems in the photolithography area of a semiconductor wafer fabrication facility

Presents the results of a simulation study for the solution of load-balancing problems in a semiconductor wafer fabrication facility. In the bottleneck area of photolithography the steppers form several different subgroups. These subgroups differ, for example, in the size of the masks that have to be used for processing lots on the steppers of a single group. During lot release it is necessary to distribute the lots over the different stepper groups in such a way that global targets like cycle time minimization, the maximization of the number of finished lots and due date performance are inside a certain range. A simulation model of a wafer fab is given that models the, photolithography area in a detailed manner. By means of this simulation model it is possible to decide at release time on which stepper subgroup processing of the lots of a certain product is favorable.