Investigation on short channel GGNMOS ESD protection device for low power IC
Eklas Hossain, Shirazush Salekin Chowdhury, Mohammad Abdul Matin, Abdelgawadf Ahmed, M. M. A. Hakim
Abstract
Eklas Hossain, Shirazush Salekin Chowdhury, Mohammad Abdul Matin, Abdelgawadf Ahmed, M. M. A. Hakim
Abstract
In this paper, the variation of trigger and hold voltages of electrostatic discharge (ESD) snapback of a 20 nm grounded-gate NMOS (GGNMOS) are analyzed by changing different parameters such as the p-well doping, gate workfunction, drain to body contact distance and external resistance added to the body contact using TCAD simulation. It was found that decreasing the body doping concentration of a 20 nm GGNMOS decreases the trigger and hold voltages. Increasing the gate work-function increases the trigger and hold voltages. The body contact with respect to drain was moved closer, as a result, the trigger and hold voltages were increased. External resistance was added to the body contact terminal and with increased resistances, the trigger and hold voltages decreased. The results inevitably show routes toward optimization and designing of a low voltage ESD protection circuit for aggressively scaled technology node.
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In this paper, the variation of trigger and hold voltages of electrostatic discharge (ESD) snapback of a 20 nm grounded-gate NMOS (GGNMOS) are analyzed by changing different parameters such as the p-well doping, gate workfunction, drain to body contact distance and external resistance added to the body contact using TCAD simulation. It was found that decreasing the body doping concentration of a 20 nm GGNMOS decreases the trigger and hold voltages. Increasing the gate work-function increases the trigger and hold voltages. The body contact with respect to drain was moved closer, as a result, the trigger and hold voltages were increased. External resistance was added to the body contact terminal and with increased resistances, the trigger and hold voltages decreased. The results inevitably show routes toward optimization and designing of a low voltage ESD protection circuit for aggressively scaled technology node.
Key concepts: Snapback, Electrostatic discharge, NMOS logic, Voltage, Materials science, Electrical engineering, Contact resistance, Optoelectronics