Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices

In this paper, we present a compact electrothermal device model which can be used to simulate NMOS devices operating in the snapback regime. By incorporating temperature dependencies in the device model and using the electrothermal circuit simulator iETSIM, we are able to simulate the second breakdown of NMOS devices under EOS stress. The NMOS model also incorporates the finite breakdown time effect which is important for simulating charge device model (CDM) ESD stress events.