Modeling NMOS snapback characteristic using PSpice

Gate-grounded NMOS is often used as ESD protection for circuit design. The ESD behavior of the NMOS transistor is based on the snapback action of its parasitic, lateral NPN BJT. Modeling this behavior of NMOS devices is very important for design of ICs, because there are no standard models, which can be used for describing high current regions in the NMOS snapback characteristic. In this paper an approach of modeling snapback characteristic of NMOS device, intended for use as ESD clamp in IC I/O cells, is proposed. The modeled snapback characteristic is simulated and evaluated using PSPICE.