Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow

SystemC-based Virtual Prototypes (VPs) are an industry-proven solution to tackle the rising complexity of embedded systems in the design flow. This paper proposes a comprehensive set of novel approaches that strongly enhance all major aspects of a modern VP-based design flow. A strong emphasis is put on automated formal verification methods and advanced coverage-guided testing techniques tailored for SystemC-based VPs and also the software. In addition, we consider VP modeling techniques that cover functional as well as non-functional aspects and also propose automated correspondence analyses between the hardware-and VP-level to utilize information available at different levels of abstraction. All approaches have been extensively evaluated with several experiments that clearly demonstrate their effectiveness in strongly enhancing the VP-based design flow, in particular by drastically improving the overall quality in combination with a reduction in time-to-market. Furthermore, this paper puts a particular focus on the modern RISC-V Instruction Set Architecture (ISA).