2020Advances in intelligent systems and computingRequires access

High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware

Paresh Baidya, Rourab Paul, Suman Sau

Open publisher page 1 citations

Abstract

This record does not include an abstract. Use the full-text link above if available.

About this research paper

What this paper is about

An abstract is not available in the OpenAlex record for this paper.

Why it matters

OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Key concepts: Field-programmable gate array, Application-specific integrated circuit, VHDL, Computer science, Embedded system, Computer architecture, Throughput, FPGA prototype

Related papers

Back to paper searchBrowse research topicsOriginal source
High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware — Research Paper | ScholarLens