2003Unpublished venueRequires access

Accurate VHDL libraries for ASIC design

Jianlu Wu, Tzay Y. Young, Eiji Kawamoto, W. Keutgens

Open publisher page 1 citations

Abstract

The creation of a VHSIC hardware description language (VHDL) library with sign-off quality for a 0.8- mu m CMOS ASIC technology is described. The methodology used, the problems encountered, and accuracy and performance are discussed.>

About this research paper

What this paper is about

The creation of a VHSIC hardware description language (VHDL) library with sign-off quality for a 0.8- mu m CMOS ASIC technology is described. The methodology used, the problems encountered, and accuracy and performance are discussed.>

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OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

The creation of a VHSIC hardware description language (VHDL) library with sign-off quality for a 0.8- mu m CMOS ASIC technology is described. The methodology used, the problems encountered, and accuracy and performance are discussed.>

Key concepts: VHDL, Application-specific integrated circuit, Computer science, CMOS, Hardware description language, Computer architecture, Programming language, Embedded system

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