RTL synthesis of case study using design compiler

With the exponential growth in the capacity and performance of Application Specific Integrated Circuits (ASIC), the area, timing and power consumption are the three most critical constraining factors that affect the Very Large Scale Integration (VLSI) IC design flow. The continuous increase in complexity of VLSI designs is the primary driving force for the invention of Electronic Design Automation (EDA) tools and design methodologies. Design Compiler (DC) is an EDA tool from Synopsys provides an effective means of synthesis techniques which speeds up the design cycle and enhances the design quality. Logic Synthesis plays an important role in the ASIC design flow, transforms the RTL design into gate level netlist in order to meet the timing and area goals. This paper presents the study of logic synthesis flow and performance analysis of synthesized RTL design using DC tool. The performance analysis includes the comparison of synthesis results with scan and without scan as well as with and without constraints scenarios. The netlists are verified against RTL formally for Logic Equivalence Check (LEC) using Conformal EC tool. Synthesis based test methodology is also used to increases the designer productivity.