Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment
Rolf Drechsler, Stefan Höreth, Early Code
Abstract
Rolf Drechsler, Stefan Höreth, Early Code
Abstract
This paper outlines formal verification in general and then introduces CVE's equivalence checking tool gatecomp, an equivalence checker developed in the formal verification group at Infineon, Germany. The basic verification tasks are described and the advanced features of the tool are discussed. The application of gatecomp to large industrial examples is reported. This demonstrates the power of the tool for various verification tasks, like netlist vs netlist comparison, RTL vs. netlist comparison or RTL vs. RTL comparison.
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This paper outlines formal verification in general and then introduces CVE's equivalence checking tool gatecomp, an equivalence checker developed in the formal verification group at Infineon, Germany. The basic verification tasks are described and the advanced features of the tool are discussed. The application of gatecomp to large industrial examples is reported. This demonstrates the power of the tool for various verification tasks, like netlist vs netlist comparison, RTL vs. netlist comparison or RTL vs. RTL comparison.
Key concepts: Netlist, Formal equivalence checking, Computer science, Equivalence (formal languages), Formal verification, Model checking, Programming language, Intelligent verification