Investigation of ruggedness failure and UIS performance improvement by using drain engineering technique in UHV-JFET
Suman Jaiswal, Gene Sheu, Ming-Che Yang, Syed Neyaz Imam, Po‐An Chen
Abstract
Suman Jaiswal, Gene Sheu, Ming-Che Yang, Syed Neyaz Imam, Po‐An Chen
Abstract
This paper investigates the failure mechanism of Ultra High Voltage JFET (UHV-JFET) under Unclamped Inductive Switching (UIS) test. We explain the ruggedness failure of the Power MOSFETs based on drain impact ionization event, diffusion current flowing through the impact ionization area enhancing the impact ionization level. An optimum drain engineering technique based on device structure and implantation method indicates that the avalanche current and avalanche energy capability per micron width can be enhanced up to 27% and 67% respectively.
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This paper investigates the failure mechanism of Ultra High Voltage JFET (UHV-JFET) under Unclamped Inductive Switching (UIS) test. We explain the ruggedness failure of the Power MOSFETs based on drain impact ionization event, diffusion current flowing through the impact ionization area enhancing the impact ionization level. An optimum drain engineering technique based on device structure and implantation method indicates that the avalanche current and avalanche energy capability per micron width can be enhanced up to 27% and 67% respectively.
Key concepts: JFET, Impact ionization, Materials science, Ionization, Voltage, Optoelectronics, Failure mechanism, Avalanche breakdown