Design And Implementation Of High Speed Complex Multiplier Using Fpga

Multiplication is an important part in real-time digital signal processing (DSP). The present work deals with the design and implement of complex ultiplier/mixer using Field Programmable Gate Array (FPGA) chip with low cost and high speed. Two devices of FPGA are chosen to implement the design; to achieve the task of mixer system implementation. The rules that are important for such implementation are proposed in order to reach the minimum cost and high speed requirement for the individual component of mixer system. These components are software simulated using VHDL language, with software called MODELSIM version SE-EE5.4a. Since mixer is important in any digital receiver because of high speed need, so different multiplier method are proposed with different data resolution and different worst case of additional noise. To achieve high speed data, a parallel tree multiplier is used with Wallace tree method which is optimal in speed but it has a complicated routing that makes it impractical to implement, because of this, we present a modification for fast parallel multiplier using both Wallace tree and Booth algorithm to achieve a sufficient design for most of DSP application. The proposed design of mixer is simulated using ISE4.1i and results in successful achievement of its desired specification. The final implementation of programmable (4, 8, 16, 32 and 64) bit mixer data input resolution is achieved using Virtex-II devices and also implemented in LP-2900 CPLD device. The resulting performance depending on multiplier method are viewed in mixer cost. However, the routing is much more regular with great reduction in FPGA cost and it is achieved for the desired mixer when compared with other methods.