Sun De
Abstract
The design of an 8 bit parallel multiplier using MAX+PLUS II software and FLEX10K10 in Altera's FPGA is presented in the paper Device simulation is performed, which validates the design
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The design of an 8 bit parallel multiplier using MAX+PLUS II software and FLEX10K10 in Altera's FPGA is presented in the paper Device simulation is performed, which validates the design
Key concepts: Multiplier (economics), Field-programmable gate array, Bit (key), Computer science, 8-bit, Electronic engineering, Arithmetic, Parallel computing