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2017•Unpublished venueRequires access

A low dropout regulator with enhanced power supply rejection and stability

Amin Pourvali Kakhki, Mohammad Maymandi‐Nejad

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Abstract

In this paper a low dropout (LDO) regulator with enhanced power supply rejection (PSR) and increased phase margin (PM) using the bulk driven transistor technique is presented. Compared to other LDOs, the proposed regulator adjusts its performance based on the load current such that the PM and PSR are improved in a relatively large range of load currents. In the LDO a signal which is dependent on the load current is generated and applied to the bulk of the passing transistor to enhance the PSR. Moreover, the proposed technique leads to a right half plane (RHP) zero in the loop gain and increases the PM. The proposed LDO is designed to operate by a 1.2 V supply voltage and to generate an output voltage of 1 V. The maximum load current is 20 mA and it is designed in the 0.13-µm CMOS technology.

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What this paper is about

In this paper a low dropout (LDO) regulator with enhanced power supply rejection (PSR) and increased phase margin (PM) using the bulk driven transistor technique is presented. Compared to other LDOs, the proposed regulator adjusts its performance based on the load current such that the PM and PSR are improved in a relatively large range of load currents. In the LDO a signal which is dependent on the load current is generated and applied to the bulk of the passing transistor to enhance the PSR. Moreover, the proposed technique leads to a right half plane (RHP) zero in the loop gain and increases the PM. The proposed LDO is designed to operate by a 1.2 V supply voltage and to generate an output voltage of 1 V. The maximum load current is 20 mA and it is designed in the 0.13-µm CMOS technology.

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Available abstract

In this paper a low dropout (LDO) regulator with enhanced power supply rejection (PSR) and increased phase margin (PM) using the bulk driven transistor technique is presented. Compared to other LDOs, the proposed regulator adjusts its performance based on the load current such that the PM and PSR are improved in a relatively large range of load currents. In the LDO a signal which is dependent on the load current is generated and applied to the bulk of the passing transistor to enhance the PSR. Moreover, the proposed technique leads to a right half plane (RHP) zero in the loop gain and increases the PM. The proposed LDO is designed to operate by a 1.2 V supply voltage and to generate an output voltage of 1 V. The maximum load current is 20 mA and it is designed in the 0.13-µm CMOS technology.

Key concepts: Low-dropout regulator, Dropout voltage, Load regulation, Regulator, Phase margin, CMOS, Transistor, Control theory (sociology)

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