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2021•2021 14th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)Requires access

A Capacitor-Free Low-Dropout Regulator with Low Line Regulation Rate and High Stability

Yimin Liang, Shengxi Diao

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Abstract

A Capacitor-Free Low-Dropout Regulator(LDO) for power adapter with an input voltage range of 8V∼24V is presented in this paper. The proposed LDO structure uses a high voltage to low voltage circuit (H2L) to convert the input voltage to a voltage less than 5V, effectively avoiding transistor breakdown and reducing line regulation rate. To solve the stability problem of capacitor-free LDO, the damping-factor-control(DFC) frequency compensation is adopted to enhance stability. The proposed LDO has been implemented in a 0.18um CMOS technology, and the active chip area is 220um*120um(Without PAD). The maximum load current of the LDO is 100mA. The LDO ensures stability over a range of load variations from 0 to 100mA. The line regulation rate is 0.37mV/V.

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What this paper is about

A Capacitor-Free Low-Dropout Regulator(LDO) for power adapter with an input voltage range of 8V∼24V is presented in this paper. The proposed LDO structure uses a high voltage to low voltage circuit (H2L) to convert the input voltage to a voltage less than 5V, effectively avoiding transistor breakdown and reducing line regulation rate. To solve the stability problem of capacitor-free LDO, the damping-factor-control(DFC) frequency compensation is adopted to enhance stability. The proposed LDO has been implemented in a 0.18um CMOS technology, and the active chip area is 220um*120um(Without PAD). The maximum load current of the LDO is 100mA. The LDO ensures stability over a range of load variations from 0 to 100mA. The line regulation rate is 0.37mV/V.

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Available abstract

A Capacitor-Free Low-Dropout Regulator(LDO) for power adapter with an input voltage range of 8V∼24V is presented in this paper. The proposed LDO structure uses a high voltage to low voltage circuit (H2L) to convert the input voltage to a voltage less than 5V, effectively avoiding transistor breakdown and reducing line regulation rate. To solve the stability problem of capacitor-free LDO, the damping-factor-control(DFC) frequency compensation is adopted to enhance stability. The proposed LDO has been implemented in a 0.18um CMOS technology, and the active chip area is 220um*120um(Without PAD). The maximum load current of the LDO is 100mA. The LDO ensures stability over a range of load variations from 0 to 100mA. The line regulation rate is 0.37mV/V.

Key concepts: Low-dropout regulator, Dropout voltage, Line regulation, Capacitor, Voltage regulator, Load regulation, Control theory (sociology), Linear regulator

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