Implementation of the AES Realization Method On Reconfigurable Hardware

Abstract—This paper presents a VLSI implementation of the Advanced Encryption Standard (AES) algorithm. The AES is a Federal Information Processing Standard (FIPS), which is a cryptographic algorithm that is used to protect digital data. AES encryption and decryption requires a 128 bit wide input block and a 128 bit wide input key. Under the influence of a key schedule the input block is encrypted by transforming it in a unique way into a new block of same size. The major emphasis is on presenting a power and moreover an area optimized AES. For implementing AES Rijndael algorithm on FPGA we will choose VHDL as the design entry technique. Xilinx ISE Design Suite version 14.7 will be used for the Synthesis and Simulation of the code.