Optimized and Configurable Hardware Implementation of AES Algorithm

The Advanced Encryption Standard (AES) is new symmetric block encryption standard,it is widely applied to government section and commerce organization. Firstly,AES algorithm is introduced in this paper. Then the key features and challenges of AES algorithm implementation of hardware are analyzed. Finally, the circuit of AES algorithm is implemented on Xilinx VirtexII XC2V3000-4 device. A optimized structure of non-pipelined data path of AES is described in this paper. We offer a new and configurable structure of on-flying-key scheduler with 128?192 and 256 bit cipher key. Furthermore, our design can configure four modes of AES operation. Results obtained show that this design has better performance than other FPGA implementation of AES.