FPGA implementation of advanced Encryption Standard algorithm

An AES is the most popular security algorithm and it is required to improve the performance of AES with increasing the demand of internet security. AES is a symmetric key algorithm in which only one key is requires for encryption and decryption process, key must be same. The AES implementation is possible for software and hardware but hardware implementation has better speed in comparison to software. In the proposed work, we implemented AES on FPGA as it provides reconfigurable hardware to verify the real-time implementation. The proposed design uses repetitive looping method with 128 bits block size and key size. AES implementation of our design is also compared with other designs to show the hardware utilization.