A new low-power 1-Bit CMOS full-adder cell based on multiplexer

This paper presents a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and lowpower consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDPis 30% less than SS16T full- adder. We have compared two full-adders, 14T and SS16T, withour proposed full-adder. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.