Implementation of Novel Ultra-Low Power and High-Speed 1-Bit Full Adder Cell

2 Abstract: This paper presents a novel ultra-low power and high speed 1-bit Full-Adder, which is designed only based on pass transistor logic. The main advantages of this design are very low propagation delay and ultra-low consumption power, which lead to achieve lower PDP and EDP than that of other. Intensive HSPICE simulation indicates that the new Full-Adder consumes around 70% less power than 14T Adder, moreover its EDP 83% is lesser than 28T Full-Adder. We have compared some of the most popular Full-Adders like 28T, CPL, SS16T, 10T, and 14T to the proposed Full-Adder. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.