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2003•Unpublished venueRequires access

A 5 volt high density poly-poly erase flash EPROM cell

R. Kazerounian, S. Ali, Yubin Ma, B. Eitan

Open publisher page 16 citations

Abstract

A 5-V-only flash EPROM (erasable programmable read-only memory) cell is described which is programmed by channel-hot-electron injection and erased through a poly-poly oxide. The cell consists of a self-aligned split-gate EPROM and a polysilicon erase line. A charge-pumping technique which takes advantage of very low programming current is used to ensure fast programming at a worst case condition of 125 degrees C and 4.5-V supply. An over-erase technique is used to achieve a uniform erase, high read current, and extended endurance. The flash cell is implemented in a staggered virtual ground-array which yields a cell size of 18 mu m with 1.2- mu m design rules in a double-poly CMOS EPROM process.>

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What this paper is about

A 5-V-only flash EPROM (erasable programmable read-only memory) cell is described which is programmed by channel-hot-electron injection and erased through a poly-poly oxide. The cell consists of a self-aligned split-gate EPROM and a polysilicon erase line. A charge-pumping technique which takes advantage of very low programming current is used to ensure fast programming at a worst case condition of 125 degrees C and 4.5-V supply. An over-erase technique is used to achieve a uniform erase, high read current, and extended endurance. The flash cell is implemented in a staggered virtual ground-array which yields a cell size of 18 mu m with 1.2- mu m design rules in a double-poly CMOS EPROM process.>

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OpenAlex reports 16 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A 5-V-only flash EPROM (erasable programmable read-only memory) cell is described which is programmed by channel-hot-electron injection and erased through a poly-poly oxide. The cell consists of a self-aligned split-gate EPROM and a polysilicon erase line. A charge-pumping technique which takes advantage of very low programming current is used to ensure fast programming at a worst case condition of 125 degrees C and 4.5-V supply. An over-erase technique is used to achieve a uniform erase, high read current, and extended endurance. The flash cell is implemented in a staggered virtual ground-array which yields a cell size of 18 mu m with 1.2- mu m design rules in a double-poly CMOS EPROM process.>

Key concepts: EPROM, Flash (photography), Flash memory, Electrical engineering, EEPROM, Non-volatile memory, Computer science, Hot-carrier injection

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