Area and delay efficient carry select adder using carry prediction approach

Various approaches and designs of digital arithmetic units have been proposed in the recent years and their merits and demerits have been compared on various performance parameters.In modern day digital systems, Arithmetic and Logic Unit operations on reconfigurable devices are the most important area of research.In this paper, a novel design for Carry Select Adder is proposed.In the design, the half adder of both the ripple carry adders is shared and an initial sum and carry is generated.The carry input module generates the 'carry' values and are passed through multiplexer in first method or xor-ed with the sum in the second method.The novel approach is then compared with the existing approaches in the literature and results show that the proposed approach outperforms all the previous approaches on the basis of delay and area complexity.The proposed approach shows significant improvement in both number of slices used and the combinational path delay.