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2012•Journal of the Institute of Electronics Engineers of KoreaRequires access

Phase Locked Loop with Analog Band-Selection Loop

Sang Ki Lee, Young-Shig Choi

Open publisher page 1 citations

Abstract

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V CMOS process and proved by HSPICE simulation.

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What this paper is about

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V CMOS process and proved by HSPICE simulation.

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OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V CMOS process and proved by HSPICE simulation.

Key concepts: Phase-locked loop, PLL multibit, Loop (graph theory), Delay-locked loop, Lock (firearm), Phase noise, Bandwidth (computing), Computer science

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