An adaptive bandwidth phase locked loop with locking status indicator

This paper presents a new structure of phase locked loop (PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and locking status indicator (LSI). The LSI decides the operating bandwidth of loop filter. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than 100/spl mu/s and spur is -60dBc. It is simulated by HSPICE in a CMOS 0.35/spl mu/m process. Supply voltage and operating frequency are 3.3V and 1.28GHz, respectively.