One Improved CORDIC Algorithm of Calculating 32 bit Floating the Arctangent Functions with FPGA

Through the study of algorithms implements of the arctangent function, proposed a hierarchical carry lookahead adder structure as the basic unit of iterations basing on traditional CORDIC algorithms, double clock input, completed the ASIC circuit design of the arctangent function. The algorithm applied TSMC 55 nm process and achieved a comprehensive in Synopsys/syn 10.12 environment. The key way of the algorithm was reduced from 2.9 ns to 1.3 ns, the highest operation frequency is able to reach 769 MHz, the speed of the whole system was twice more than the original design.