Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation

This work explores approximation in CORDIC architectures for CMOS ASIC implementation. Coarse grain reduction in the number of iterations and bit-width are systematically evaluated to drive power efficiency in detriment of controlled magnitude error occurrence for the trigonometric sine and cosine functions. The approximate versions of the proposed CORDIC architecture are described in VHDL and synthesized for a 45 nm technology. Results indicate that for error-tolerant applications, where the number of iterations can be lower than the number of bits, significant power reduction can be achieved.