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Implementation of a Complete Synchronization Digital Frequency Meter Based on FPGA

Tan Yong-hong

Open publisher page 3 citations

Abstract

A complete synchronization digital frequency meter is designed using FPGA chip by VHDL language programming according to the complete synchronization measurement theory.It eliminates ±1 count error with an accurate frequency-measuring range of DC~100 MHz.This paper gives the design approach by VHDL and the simulation waveform of every module of the meter.A system board can be made with the FPGA chip,which has higher practicability and reliability.

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What this paper is about

A complete synchronization digital frequency meter is designed using FPGA chip by VHDL language programming according to the complete synchronization measurement theory.It eliminates ±1 count error with an accurate frequency-measuring range of DC~100 MHz.This paper gives the design approach by VHDL and the simulation waveform of every module of the meter.A system board can be made with the FPGA chip,which has higher practicability and reliability.

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OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A complete synchronization digital frequency meter is designed using FPGA chip by VHDL language programming according to the complete synchronization measurement theory.It eliminates ±1 count error with an accurate frequency-measuring range of DC~100 MHz.This paper gives the design approach by VHDL and the simulation waveform of every module of the meter.A system board can be made with the FPGA chip,which has higher practicability and reliability.

Key concepts: VHDL, Field-programmable gate array, Synchronization (alternating current), Computer science, Waveform, Metre, Computer hardware, Reliability (semiconductor)

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