Bo Zhao
Abstract
This paper discusses the theory of AES algorithm,and describes its process and structure with Verilog HDL.Based on the structure,it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits.When the system clock frequency is 25MHz,the encryption speed of the design is 3Gbits/s which reaches the top level in the world.
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This paper discusses the theory of AES algorithm,and describes its process and structure with Verilog HDL.Based on the structure,it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits.When the system clock frequency is 25MHz,the encryption speed of the design is 3Gbits/s which reaches the top level in the world.
Key concepts: Computer science, Advanced Encryption Standard, Field-programmable gate array, Verilog, Encryption, Block (permutation group theory), Embedded system, Computer hardware