Optimized Design of AES Encryption Based on FPGA

This paper principally presents the optimized design of FPGA-based AES algorithm, and describes the AES algorithm, the Rijndael algorithm, optimization of AES algorithm, the realization of AES cipher based on FPGA, the communication programmable logic device function of PC and FPGA, including the realization of Rijndeal algorithm based on FPGA technology. Finally it gives various corresponding simulation results and waveforms output.