Design and simulation of UART module based on Verilog HDL

UART(Universal Asynchronous Receiver Transmitter)is applied to data exchange between the microcomputer and peripherals,according to the characteristics of the UART,this paper puts forward an UART design method based on Verilog HDL.Top-down design process is researched,uses the description form of FSM,Verilog HDL is used to design the salve module and the top module of UART,so it can make whole design tighter and more reliable.The system compatibility is enhancing due to the parametric design method.The simulate results indicate that the UART design can be used in situations such as transmission using standard asynchronous serial RS-232 protocol and integrate into the FPGA chip to use.