Guofeng Li
Abstract
In this paper, we address a method of the hardware realization for floating point multiplier with VHDL. That is, the multiplier is described with VHDL, realized on FPGA. We have done the simulation in MAX+plus2 and got very good results. We can do multiplication of arbitrary bits with it.
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In this paper, we address a method of the hardware realization for floating point multiplier with VHDL. That is, the multiplier is described with VHDL, realized on FPGA. We have done the simulation in MAX+plus2 and got very good results. We can do multiplication of arbitrary bits with it.
Key concepts: VHDL, Multiplier (economics), Field-programmable gate array, Realization (probability), Computer science, Floating point, Computer hardware, Arithmetic