ScholarLens Back to search
2014•International Journal of Innovative Research in Electronics and CommunicationsRequires access

Implementation of Double Precision Floating Point Multiplier in VHDL

Gargi S. Rewatkar

Open publisher page 0 citations

Abstract

This record does not include an abstract. Use the full-text link above if available.

About this research paper

What this paper is about

An abstract is not available in the OpenAlex record for this paper.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Key concepts: Computer science, Multiplier (economics), VHDL, Arithmetic, Computer hardware, Mathematics, Field-programmable gate array, Economics

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Implementation of Double Precision Floating Point Multiplier in VHDL — Research Paper | ScholarLens