The Design of Finite State Machine Based on VHDL

VHDL((Very High speed Integrated Lircuit) Hardware Description Language) is one of the key techniques of EDA(Electronic Design Automation).FSM(Finite State Machine) is a significant way to achieve the logical control with high efficiency and reliability.The process of modulo-4 forward-backward counter based on VHDL and CPLD EP1C3TC144 are stated,The application of VHDL and MAX+plusII in the modern digital system design is introduced in detail.The methods and procedures of the FSM design based on VHDL are presented in this paper.The problems in the design are also disscussed.The modulo-4 forward-backward counter based on FSM effectively eliminates the burr of pulse in counter,and is validated on EP1C3TC144.