Study on the Design of Finite State Machine by VHDL

The finite state machine and its design technology are the important part of the design of the practical digital system.The method of description of finite state machine(FSM) with VHDL is presented.The author researched how to synthesize the program of FSM based on VHDL through synplify pro7.6.Using a example of the designing process of Memory Controller with VHDL,the author summary the design method of FSM with VHDL.