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Verilog Design and Research of Finite State Machine

Yuzhuo Fu

Open publisher page 1 citations

Abstract

This paper studies different state encoding styles and Verilog descriptions of Finite State Machine (FSM). Based on these styles, benefits and shortages are described. Furthermore, as a FSM design example, a DMA Arbiter is presented and implemented in seven ways discussed in this paper. The timing and area results of Design Compiler synthesis are also analyzed.

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What this paper is about

This paper studies different state encoding styles and Verilog descriptions of Finite State Machine (FSM). Based on these styles, benefits and shortages are described. Furthermore, as a FSM design example, a DMA Arbiter is presented and implemented in seven ways discussed in this paper. The timing and area results of Design Compiler synthesis are also analyzed.

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OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper studies different state encoding styles and Verilog descriptions of Finite State Machine (FSM). Based on these styles, benefits and shortages are described. Furthermore, as a FSM design example, a DMA Arbiter is presented and implemented in seven ways discussed in this paper. The timing and area results of Design Compiler synthesis are also analyzed.

Key concepts: Computer science, Finite-state machine, Arbiter, Verilog, Compiler, State (computer science), Programming language, Economic shortage

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