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2005•Journal of Military Communications TechnologyRequires access

Implementation of DVB Standard RS Encoder

Yin Xiao-fang

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Abstract

Abstrcat In this paper, a simplified design of a DVB standard RS(204,188) encoder was introduced by a simplified multiplier in GF (2~8). Its implementation in FPGA has advantages of less LE number and higher operating speed than the general ones. Finally, the design was verified by software simulation and real application. This design method may have some help to other similar designs.

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What this paper is about

Abstrcat In this paper, a simplified design of a DVB standard RS(204,188) encoder was introduced by a simplified multiplier in GF (2~8). Its implementation in FPGA has advantages of less LE number and higher operating speed than the general ones. Finally, the design was verified by software simulation and real application. This design method may have some help to other similar designs.

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Available abstract

Abstrcat In this paper, a simplified design of a DVB standard RS(204,188) encoder was introduced by a simplified multiplier in GF (2~8). Its implementation in FPGA has advantages of less LE number and higher operating speed than the general ones. Finally, the design was verified by software simulation and real application. This design method may have some help to other similar designs.

Key concepts: Computer science, Encoder, Field-programmable gate array, Multiplier (economics), Software, Computer hardware, Embedded system, Operating system

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