2007•Journal of Hefei University of TechnologyRequires access

Design of 8-bit high-performance microcontroller IP softcore

Jing Nie

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Abstract

Based on the analysis of the limitation of the MCS-51 micro controller unit(MCU),a high-performance reusable MCU IP softcore,which is compatible with MCS-51,is designed.In system architecture,the four-clock period per machine cycle architecture,the pre-fetching instruction method and the independent bus method are adopted and new arithmetic is used for addition and division,thus improving the MCU's power efficiency.Altera FPGA verification and simulation show that the presented MCU can run at 33.8 MHz clock frequency steadily.

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What this paper is about

Based on the analysis of the limitation of the MCS-51 micro controller unit(MCU),a high-performance reusable MCU IP softcore,which is compatible with MCS-51,is designed.In system architecture,the four-clock period per machine cycle architecture,the pre-fetching instruction method and the independent bus method are adopted and new arithmetic is used for addition and division,thus improving the MCU's power efficiency.Altera FPGA verification and simulation show that the presented MCU can run at 33.8 MHz clock frequency steadily.

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Available abstract

Based on the analysis of the limitation of the MCS-51 micro controller unit(MCU),a high-performance reusable MCU IP softcore,which is compatible with MCS-51,is designed.In system architecture,the four-clock period per machine cycle architecture,the pre-fetching instruction method and the independent bus method are adopted and new arithmetic is used for addition and division,thus improving the MCU's power efficiency.Altera FPGA verification and simulation show that the presented MCU can run at 33.8 MHz clock frequency steadily.

Key concepts: Microcontroller, Embedded system, Field-programmable gate array, Computer science, 32-bit, Computer hardware, Controller (irrigation), Division (mathematics)

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