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Design of a High-Efficiency MCS51 Compatible MCU Core

Hao Yang

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Abstract

Based on the analysis of the limitation of the MCS51 MCU, a high-efficiency and low-power MCU, which is compatible with MCS51, is designed. The efficiency of the instruction is improved by 12 times by optimizing the pipeline structure and two phase clock. The instruction set is extended in order to improve the efficiency in particular application. The MCU supply the sleep-mode to decrease the power consumption by adds a new power management controller. Altera FPGA verification and simulation shows that the MCU can run at 33MHz clock frequency steadily.

About this research paper

What this paper is about

Based on the analysis of the limitation of the MCS51 MCU, a high-efficiency and low-power MCU, which is compatible with MCS51, is designed. The efficiency of the instruction is improved by 12 times by optimizing the pipeline structure and two phase clock. The instruction set is extended in order to improve the efficiency in particular application. The MCU supply the sleep-mode to decrease the power consumption by adds a new power management controller. Altera FPGA verification and simulation shows that the MCU can run at 33MHz clock frequency steadily.

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Available abstract

Based on the analysis of the limitation of the MCS51 MCU, a high-efficiency and low-power MCU, which is compatible with MCS51, is designed. The efficiency of the instruction is improved by 12 times by optimizing the pipeline structure and two phase clock. The instruction set is extended in order to improve the efficiency in particular application. The MCU supply the sleep-mode to decrease the power consumption by adds a new power management controller. Altera FPGA verification and simulation shows that the MCU can run at 33MHz clock frequency steadily.

Key concepts: Microcontroller, Computer science, Pipeline (software), Embedded system, Field-programmable gate array, Power (physics), Power consumption, Computer hardware

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