2015•Information technology newsletterRequires access

64-order FIR filter distributed arithmetic optimization and its implementation

Tang Qiao-zh

Abstract

This paper discusses on the 64-order FIR filter design based on the distributed arithmetic of FPGA. And the improvement program of distributed arithmetic is detailed studied. Finally,the simulation design of FIR filter is completed by means of full parallel distributed arithmetic and dividing LUT. The simulation results show that the improvement program meets the design requirements.

About this research paper

What this paper is about

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Key concepts: Finite impulse response, Computer science, Arithmetic, Lookup table, Field-programmable gate array, Filter (signal processing), Order (exchange), Parallel computing