A FPGA Design of FFT Algorithm

This paper introduces a FPGA design scheme of the Radix-4 DIF FFT algorithm base on FFT Algorithm.In the FPGA implementation of FFTs,the computation of butterflies contains many twiddle factor multiplications.An improvement method is presented to reduce the multiplication number and memory space of twiddle factors,which hence speeds up the butterfly computation.The design of address mapping can get position of data without calculation.In combination of using the structure of ping-pang RAM and the pipelining,the speed of the FFT′s FPGA implementation can be increased,which provides some reference for the implementation of FFT.