Soft-Decision Viterbi and Sequential Decoding on FPGA

FPGA implementations of a Viterbi decoder and a Sequential decoder are presented, in which the same code rate 1/2, constraint length 7 and 3bit soft decision are adopted. Based on FPGA implementations, decoding performances of Viterbi decoder and Sequential decoder have been tested and compared with each other. It is shown that, with comparable decoding speed performance and a slight coding gain loss, the sequential decoder consumes much lower resource usage than Viterbi decoder. However, this is at the cost of an increased decoding delay.