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Design of High-speed FIR Filter Based on FPGA

Jiang Zhu

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Abstract

To realize filtering of high-speed input data,and aiming at the design method of systolic FIR digital filter,this paper proposes a design method of high-speed FIR filter based on FPGA.The implementation of this design is illustrated by the process of designing a 16-tap FIR digital filter using VHDL language.Simulation by Modelsim shows that the design is feasible and can support high-speed data of 1 GSPS.

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What this paper is about

To realize filtering of high-speed input data,and aiming at the design method of systolic FIR digital filter,this paper proposes a design method of high-speed FIR filter based on FPGA.The implementation of this design is illustrated by the process of designing a 16-tap FIR digital filter using VHDL language.Simulation by Modelsim shows that the design is feasible and can support high-speed data of 1 GSPS.

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Available abstract

To realize filtering of high-speed input data,and aiming at the design method of systolic FIR digital filter,this paper proposes a design method of high-speed FIR filter based on FPGA.The implementation of this design is illustrated by the process of designing a 16-tap FIR digital filter using VHDL language.Simulation by Modelsim shows that the design is feasible and can support high-speed data of 1 GSPS.

Key concepts: ModelSim, VHDL, Field-programmable gate array, Finite impulse response, Filter (signal processing), Half-band filter, Computer science, Filter design

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