High Order FIR Filter Based on Distributed Arithmetic and Its FPGA Implementation

As Field Programmable Gate Array(FPGA) technology has been steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing(DSP) application. To solve the problem that implementation of high order FIR filter consumes rather more hardware resources in FPGA, the bit-serial distributed arithmetic based on multiple look-up tables is presented. A 32-tap 8-bit order low pass FIR filter is taken as an example to illustrate the method. Simulation shows that the method saves much more resources in FPGA,and improves the performance of FIR filter to some extent.