Optimized implementation scheme of three phase phase-locked loop based on FPGA

An optimized implementation scheme of FPGA based digital three phase phase-locked loop which fits in electric power system is presented in this paper. At first, this paper introduces basic architecture and principle of this phase-locked loop including phase discriminator, loop filter and voltage controlled oscillator (VCO), etc. Then this design of phase-locked loop is optimized in order to save the logic source of FPGA by optimization scheme of sharing space. A new method, which is combined with CORDIC algorithm and look-up table is proposed to generate sine function. This method could increase computing speed and guarantee the accuracy of results at the same time. At last, this design is implemented on ALTERA’s FPGA Cyclone EP1C12Q240C8. The results verify that this system could reduce the usage of logic resource of FPGA and track the variation of frequency and lock the base phase well.