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Design of Path Metric Memory Unit with Longer Constrain Length in Viterbi Decoder

Xin Chen

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Abstract

Based on the high forward error correction performance,a Viterbi decoder has been widely utilized in communication applications.A FPGA implementation of Viterbi decoder,which has two influence aspects of hardware resource and speed,it can deduce the conflict through the effected arrange ACS unit and path metric memory.Base on the radix-4,a path metric memory is proposed to improve the speed and deduce hardware resources.

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What this paper is about

Based on the high forward error correction performance,a Viterbi decoder has been widely utilized in communication applications.A FPGA implementation of Viterbi decoder,which has two influence aspects of hardware resource and speed,it can deduce the conflict through the effected arrange ACS unit and path metric memory.Base on the radix-4,a path metric memory is proposed to improve the speed and deduce hardware resources.

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Available abstract

Based on the high forward error correction performance,a Viterbi decoder has been widely utilized in communication applications.A FPGA implementation of Viterbi decoder,which has two influence aspects of hardware resource and speed,it can deduce the conflict through the effected arrange ACS unit and path metric memory.Base on the radix-4,a path metric memory is proposed to improve the speed and deduce hardware resources.

Key concepts: Viterbi decoder, Viterbi algorithm, Computer science, Path (computing), Soft output Viterbi algorithm, Metric (unit), Soft-decision decoder, Field-programmable gate array

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Design of Path Metric Memory Unit with Longer Constrain Length in Viterbi Decoder — Research Paper | ScholarLens