ScholarLens Back to search
2005•Telecommunication EngineeringRequires access

Optimized Architectural Design of Viterbi Decoder

Huanzhang Lu

Open publisher page 0 citations

Abstract

When Viterbi algorithm is implemented in FPGA, the occupation of hardware resource and the speed of decoder are two conflictive aspects. And it can be resolved by arranging ACS unit and path metric RAM reasonably. In the case of (2,1,6) code and based on radix-4 algorithm, a new dynamic management of path metric memory is introduced, which can deduce the decoder's complexity effectively and improve the speed of Viterbi decoder relatively.

About this research paper

What this paper is about

When Viterbi algorithm is implemented in FPGA, the occupation of hardware resource and the speed of decoder are two conflictive aspects. And it can be resolved by arranging ACS unit and path metric RAM reasonably. In the case of (2,1,6) code and based on radix-4 algorithm, a new dynamic management of path metric memory is introduced, which can deduce the decoder's complexity effectively and improve the speed of Viterbi decoder relatively.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

When Viterbi algorithm is implemented in FPGA, the occupation of hardware resource and the speed of decoder are two conflictive aspects. And it can be resolved by arranging ACS unit and path metric RAM reasonably. In the case of (2,1,6) code and based on radix-4 algorithm, a new dynamic management of path metric memory is introduced, which can deduce the decoder's complexity effectively and improve the speed of Viterbi decoder relatively.

Key concepts: Soft-decision decoder, Viterbi decoder, Viterbi algorithm, Computer science, Soft output Viterbi algorithm, Path (computing), Field-programmable gate array, Decoding methods

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Optimized Architectural Design of Viterbi Decoder — Research Paper | ScholarLens