Design of Zig Bee frequency divider based on 0.18 μm CMOS technology

To reduce the energy consumption of ZigBee frequency divider,an ultra-low power CMOS frequency divider is proposed,which can be used in the frequency synthesizer of 2.45 GHz integer frequency division phase locked loop and Zig Bee standard network. Based on the swallow pulse divider,a swallow counter is replaced by a simple digital circuit to reduce the power consumption and design complexity. The modulus of the divider can be adjusted from 481 to 496. All circuits design is based on TSMC CMOS technology of 0.16 μm,in which the circuit is supplied with 1.8 V DC voltage. The simulation results show that the power consumption of the 4 bits divider is 420 μW in 2.45 GHz ISM band,and reduced by 40% in comparison with that of the previous similar frequency divider.